As a prior art maximum length shift register sequence generator ( hereinbelow called M sequence generator ) there is known that described in JP-A-No. 60-122071 filed June 5, 1985 by the same applicant.
However the generator described in that application has a construction, in which it is not taken into account to fabricate it in the form of an IC. That is, in the case where it is tried to fabricate it in the form of an IC, the number of stages of flipflops therein should be limited and it is desired to construct it so that a cascade connection is possible among a plurality of such M sequence generators in order to enable it to produce a long recurring sequence even in such circumstances.